svtmp package

svtmp.SVTMP_INDENTATION_WIDTH = 3: indentation width in spaces for all templates in svtmp.

svtmp.INDENT = ' ': default indentation for all templates in svtmp. INDENT = SVTMP_INDENTATION_WIDTH * ' '

svtmp.header(name, fname, desc, prj)[source]

generates a SystemVerilog file header.

The generated header automatically picks up the date of creation and if possible, the Camino project where the file is created.

Example:

>>> print(header(name='dtop', fname='dtop.sv', desc='Digital Top Level', prj='myproject'))

/*------------------------------------------------------------------------------
 |  Title   : dtop
 |  Project : myproject
 +------------------------------------------------------------------------------
 |  Automatically generated with svtmp python library
 |
 +------------------------------------------------------------------------------
 |  Description:
 |  Digital Top Level
 +------------------------------------------------------------------------------
 | File     : dtop.sv
 | Language : SystemVerilog
 | Created  : 2022-10-15
 +------------------------------------------------------------------------------
 |  Copyright (c) Infineon Technologies AG 2022 -  Confidential
 +------------------------------------------------------------------------------
 */

Parameters

name (str) – the name of the package/module implemented in the file.
fname (str) – filename where the header will be included.
desc (str) – short description of the file contents.
prj (str) – project for file. If None, project name will be picked up from Camino env variable SUBPROJECTNAME.

Returns

a string containing the header.

Return type

str

svtmp.ui2b(x, nbits)[source]

converts unsigned integers to SystemVerilog binary literals.

Example:

>>> ui2b(63, 8)
"8'b00111111"

Parameters

x (int) – integer input (assumed unsigned).
nbits (int) – number of bits of the SystemVerilog literal.

Returns

a string with the SystemVerilog binary literal.

Return type

str

svtmp.sui2b(x, nbits)[source]

converts unsigned integer strings to SystemVerilog binary literals.

Example:

>>> sui2b('63', 8)
"8'b00111111"

Parameters

x (str) – integer input (assumed unsigned).
nbits (int) – number of bits of the SystemVerilog literal.

Returns

a string with the SystemVerilog binary literal.

Return type

str

svtmp.ui2h(x, nbits)[source]

converts unsigned integers to SystemVerilog hex literals.

Example:

>>> ui2h(63,23)
"23'h00003f"

Parameters

x (int) – integer input (assumed unsigned).
nbits (int) – number of bits of the SystemVerilog literal.

Returns

a string with the SystemVerilog binary literal.

Return type

str

svtmp.sui2h(x, nbits)[source]

converts unsigned integer stings to SystemVerilog hex literals.

Example:

>>> ui2h('63',23)
"23'h00003f"

Parameters

x (str) – integer input (assumed unsigned).
nbits (int) – number of bits of the SystemVerilog literal.

Returns

a string with the SystemVerilog binary literal.

Return type

str

svtmp.comment(comment)[source]

returns a single line comment.

Example:

>>> comment('this is a comment')
'// this is a comment'

Parameters: comment (str) – comment content.
Returns: string comment.
Return type: str

svtmp.cheader(comment)[source]

returns a commend header.

Example:

>>> print(cheader('THIS IS A COMMENT HEADER'))
//------------------------------------------------------------------------------
// THIS IS A COMMENT HEADER
//------------------------------------------------------------------------------

Parameters: comment (str) – the content of the comment header
Returns: a string with the comment header
Return type: str

svtmp.invec(name, lhs, rhs, typ='logic')[source]

generates a packed vector input port. Used to be included in a list of ports and passed as argument to module() or SVTxt.to_module()

Example:

>> invec('data_i', 7, 0)
   'input logic [7:0] data_i'

>> invec('sfr_i', 3, 0, typ = 'sfr_in')
   'input sfr_in [3:0] sfr_i'

Parameters

name (str) – input name
lhs (int | str) – left-hand-side of the vector width definition (typ. MSB)
rhs (int | str) – right-hand-side of the vector width definition (typ. LSB)
typ – port type

Return type

str

Returns: a string with the port definition

svtmp.Input(name, typ='logic')[source]

generates a single input port. Used to be included in a list of ports and passed as argument to module() or SVTxt.to_module().

Examples:

>> Input('clk_i')
   'input logic clk_i'

>> Input('reset_i', 'reset_t')
   'input reset_t reset_i'

Parameters

name (str) – input port name
typ (str) – input port type

Return type

str

Returns: a string with the port definition

svtmp.inputs(ins)[source]

short-hand function to generate a list of logic single inputs from a list of string names.

Examples:

>> inputs(['clk_i', 'reset_n_i', 'enable_i'])
   ['input logic clk_i', 'input logic reset_n_i', 'input logic enable_i']

Parameters: ins (List[str]) – list of names for the input signals
Return type: List[str]

Returns: a list of strings with the inputs definition

svtmp.Output(name, typ='logic')[source]

generates a single output port. Used to be included in a list of ports and passed as argument to module() or SVTxt.to_module().

Examples:

>> Output('clk_i')
   'output logic clk_i'

>> Output('reset_i', 'reset_t')
   'output reset_t reset_i'

Parameters

name (str) – output port name
typ (str) – output port type

Return type

str

Returns: a string with the port definition

svtmp.outvec(name, lhs, rhs, typ='logic')[source]

generates a packed vector output port. Used to be included in a list of ports and passed as argument to module() or SVTxt.to_module()

Example:

>> outvec('data_o', 7, 0)
   'output logic [7:0] data_o'

>> outvec('sfr_o', 3, 0, typ = 'sfr_out')
   'output sfr_out [3:0] sfr_o'

Parameters

name (str) – output name
lhs (int | str) – left-hand-side of the vector width definition (typ. MSB)
rhs (int | str) – right-hand-side of the vector width definition (typ. LSB)
typ – port type

Return type

str

Returns: a string with the port definition

svtmp.outputs(outs)[source]

short-hand function to generate a list of logic single outputs from a list of string names.

Example:

>> outputs(['clk_i', 'reset_n_i', 'enable_i'])
   ['output logic clk_i', 'output logic reset_n_i', 'output logic enable_i']

Parameters: outs (List[str]) – list of names for the output signals
Return type: List[str]

Returns: a list of strings with the outputs definition

svtmp.struct(typ, decls, packed=True, debug=False)[source]

generates SystemVerilog struc type definition.

Example:

>> decls = [logic('en'), logic('dis'), logvec('cnt', 7,0)]
>> print(struct(typ = 'sfr_cnt_t', decls = decls))
   typedef struct packed {
   logic en;
   logic dis;
   logic [7:0] cnt;
} sfr_cnt_t;

Parameters

typ (str) – name of the struc type
decls (Union[str, List[str]]) – newline-separated string with signal declarations, or list of strings with them
packed (bool) –
debug (bool) –

Returns: a string with the typedef struct definition

svtmp.package(name, body, debug=False)[source]

generates a SystemVerilog package.

Example:

>> lps = [localparam(c[0],c[1]) for c in (('DATAWIDTH', 16), ('ADDRWIDTH', 10) ,('OFFSET', 100))]
>> print(package(name = 'data_pkg', body = lps))
   package data_pkg;
      localparam DATAWIDTH = 16 ;
      localparam ADDRWIDTH = 10 ;
      localparam OFFSET = 100 ;
   endpackage: data_pkg

Parameters

name (str) – name of the package.
body (Union[str, List[str]]) – string or list of strings containing the body of the package.
debug (bool) –

Returns: a string with the complete SV package.

svtmp.assign(lhs, rhs, debug=False)[source]

generates an continuous assignment statement.

Example:

>> assign('a', ui2h(64,16))
   "assign a = 16'h0040;"

Parameters

lhs (str) – left-hand side of the assigment.
rhs (str) – right hand side of the assignment.
debug (bool) –

Returns: a string with the assign statement.

svtmp.const(typ, lhs, rhs, cmt='', debug=False)[source]

generates a constant declaration.

Example:

>> const(typ = 'real', lhs = 'T', rhs = 25.0 , cmt = 'this is a comment')
   'const real T = 25.0; // this is a comment;'

Parameters

typ (str) – type of the constant
lhs (str) – constant name
rhs (str) – constant value
cmt (str) – comment after constant
debug (bool) –

Returns: a constant declaration.

svtmp.parameter(lhs, rhs, mod_decl=True, debug=False)[source]

Parameters

lhs (str) –
rhs (str) –
mod_decl (bool) –
debug (bool) –

svtmp.localparam(lhs, rhs, cmt='', debug=False)[source]

Parameters

lhs (str) –
rhs (str) –
cmt (str) –
debug (bool) –

svtmp.ifdef(s)[source]

Parameters: s (str) –
Return type: str

svtmp.ifndef(s)[source]

Parameters: s (str) –
Return type: str

svtmp.define(s)[source]

Parameters: s (str) –
Return type: str

svtmp.endif()[source]

Return type: str

svtmp.Import(pkg)[source]

Parameters: pkg (str) –
Return type: str

svtmp.logvec(name, lsb, rsb, cmt='', debug=False)[source]

Parameters: debug (bool) –

svtmp.logic(name, cmt='', debug=False)[source]

Parameters

name (str) –
cmt (str) –
debug (bool) –

svtmp.decl(typ, name, cmt='', debug=False)[source]

Parameters

typ (str) –
name (str) –
cmt (str) –
debug (bool) –

svtmp.eq(lhs, rhs, block=False, debug=False)[source]

Parameters: debug (bool) –

svtmp.concat(items, debug=False)[source]

Parameters

items (List[str]) –
debug (bool) –

svtmp.If(cond, body, debug=False)[source]

Parameters

cond (str) –
body (Union[str, List[str]]) –
debug (bool) –

svtmp.ifelse(cond, tbody, fbody, debug=False)[source]

Parameters

cond (str) –
tbody (Union[str, List[str]]) –
fbody (Union[str, List[str]]) –
debug (bool) –

svtmp.always_comb(body, debug=False)[source]

Parameters

body (Union[str, List[str]]) –
debug (bool) –

svtmp.make_always_ff(clk='clk_i', reset='reset_n_i', elevel=True, rlevel=False)[source]

svtmp.always_ff(rbody, body, clk='clk_i', reset='reset_n_i', elevel=True, rlevel=False, debug=False)[source]

Parameters

rbody (Union[str, List[str]]) –
body (Union[str, List[str]]) –
clk (str) –
reset (str) –
elevel (bool) –
rlevel (bool) –
debug (bool) –

svtmp.case_item(cond, body)[source]

svtmp.citem(cond, body)[source]

svtmp.case(key, body)[source]

Parameters

key (str) –
body (Union[str, List[str]]) –

svtmp.module(name, body, ios=None, parameters=None, imports=None)[source]

Parameters

name (str) –
body (Union[List[str], str]) –
ios (Optional[Union[List[str], str]]) –
parameters (Optional[Union[List[str], str]]) –
imports (Optional[Union[List[str], str]]) –

Return type

str

svtmp.indent(fragment, spaces=' ', first=' ')[source]

takes a (potentially) multiline string or a list of strings and indents it (joining the result by newlines if the input was a list of strings)

Example 1:

>>> s = ['logic a;', 'logic b;', 'logic c;']
>>> print(indent(s, spaces = 4*' ', first = 6*' '))
      logic a;
   logic b;
   logic c;

Example 2:

>> print(indent('a\nb\nc\n'))  # with SVTMP_INDENTATION_WIDTH = 3
   a
   b
   c

Parameters

fragment (Union[List[str], str]) – string or list of strings to be indented.
spaces (str) – indentation string (normally a number of consecutive spaces) for all lines except for first.
first (str) – indentation string for first line/string in list.

Returns

a string with indented input (either indented string or newling-concatenated string with list strings indented.

Return type

str

svtmp.block(s)[source]

takes a newline separated string of commands or a list of string commands, and returns a newline separated string of indented commands, wrapped by begin-end if necessary.

Examples:

>> print(block("a = 1"))
      a = 1

>> print(block('a = 1\nb = 2'))
   begin
      a = 1
      b = 2
   end

>> stmts = ['a = 1', 'b = 2']
>> print(block(stmts))
   begin
      a = 1
      b = 2
   end

Parameters: s (Union[str, List[str]]) – a string of newline separated statements or a list of statement strings
Returns: an indented, possibly wrapped in begin-end string with the input statements
Return type: str